1. Field of the Invention
The present invention is directed in general to the field of semiconductor devices. In one aspect, the present invention relates to the fabrication of interlayer dielectric layers used in floating gate or other semiconductor device structures.
2. Description of the Related Art
Semiconductor devices typically include device components (such as transistors and capacitors) that are formed on or in a substrate as part of the front end of line (FEOL) processing. In addition, interconnect features (such as contacts, metal lines and vias) that connect the device components to the outside world are included as part of the back end of line (BEOL) integration process whereby one or more dielectric layers are formed in and between the interconnect features for purposes of electrically isolating the interconnect features and device components. To protect semiconductor devices from the charge loss/gain effects of mobile ions and other undesired impurities, the BEOL dielectric layers typically include a layer of boro-phosphorous tetra-ethyl ortho-silicate (BPTEOS) that forms all or part of the first inter-layer dielectric (ILD0), which is sometime also referred to as the pre-metal dielectric (PMD). For example, the BPTEOS layer provides a gettering function to help protect non-volatile memories (NVM) from the effects of mobile ions that can affect the data retention performance of the NVM cell(s). The BPTEOS layer can also help control the field leakage between semiconductor transistors, such as those formed in an array of transistors.
An example of such a semiconductor device is illustrated in FIG. 1, which depicts a semiconductor device 10 in which device components (such as transistors 12, 13) are formed on or in a substrate 11. The depicted device components 12, 13 shown in simplified schematic form can represent any type of transistor device (such as a MOSFET, DRAM or NVM device), and may be formed using any desired transistor fabrication sequence which forms a gate electrode and a gate dielectric layer over the substrate 11 and uses a sidewall spacer on the gate electrode to form at least part of the source/drain region(s) (not shown) in the substrate 11. With existing fabrication processes, the gettering layer is formed by depositing a BPTEOS layer 14 over the device components 12, 13. However, when deposited non-conformally, the BPTEOS layer 14 forms more thickly at the top of the device components 12, 13 and pinches off the opening, thereby forming a void region 15 in the BPTEOS layer 14. The presence of voids in the ILD0 layer can trap mobile ions that are generated in the course of subsequent processing steps, such as ions from chemical mechanical polish slurry materials used in subsequent polishing steps and from other processing and/or cleaning steps. The presence of mobile ions in the device can reduce device yield and impair performance, particularly with NVM devices. In addition, subsequent contact formation steps can create conductive stringers in the voids (e.g., tungsten stringers), thereby shorting two or more contacts together.
In addition to introducing mobile ions, the subsequent polishing steps can also reduce or eliminate the protective function provided by the BPTEOS layer 14. This can occur during planarization of the ILD0 layer, when the BPTEOS layer 14 is part of a stack of films included in the ILD0 stack and is polished off to expose at least part of the underlying semiconductor device 20, as illustrated in FIG. 2. In particular, when a chemical mechanical polish (CMP) step is used to polish the BPTEOS layer 14, variations in the CMP polish rate (as between dense and isolated areas) can remove or thin the BPTEOS layer 14 in some areas, thereby removing the gettering protective function in those areas. Even where the polish removes only part of the BPTEOS layer 14, the remaining exposed BPTEOS layer can be exposed to impurities in the atmosphere which can be trapped in the BPTEOS layer, thereby reducing its gettering efficiency.
Accordingly, a need exists for an improved process for fabricating an ILD0 layer that is void-free. In addition, there is a need for a void-free ILD0 stack that provides full gettering protection and that can be effectively, efficiently and reliably integrated into the fabrication process, such as the middle of line process. There is also a need for an improved ILD0 stack formation process that will provide effective protection against mobile ions, improve device yield and/or reduce the formation of stringer shorts. There is also a need for an improved semiconductor processes and devices to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.